Innovators Day Webinar Series: Your Guide to What’s Next in FPGA Innovation
Explore the sessions from Innovators Day 2025, as one-hour bits, and later on demand; created for engineers, architects, developers, and technical decision makers building next-generation systems.
Discover new techniques, tools, and architectures that are transforming how teams design with FPGAs. Watch keynotes and partner demos and speak with an expert that share practical ways to accelerate development, improve performance, and solve real-world challenges.
Featuring insights from Altera experts and ecosystem partners, each session delivers actionable guidance that helps you move faster and innovate with confidence.
Raghib leads Altera’s global strategy and R&D, driving growth in FPGA solutions. With over 30 years in semiconductors, he has held leadership roles at Marvell, Cavium, Cisco, and more—co-founding Cavium and helping scale it into a billion-dollar business. A Stanford Executive Program graduate with 40+ patents, Raghib serves on Cirrus Logic’s Board of Directors.
Ilya leads FPGA Architecture definition at Altera. He joined Intel in 2018 to lead Agilex FPGA core architecture development and definition of application-specific optimizations for AI, HPC, and wireless communication applications. Ilya has co-authored over 40 granted patents and dozens of publications and presentations on FPGA architectures, CAD algorithms, prefetching in memory hierarchies, and circuit design. Ilya received his Ph.D. degree in Electrical and Computer Engineering from Cornell University.
Founder & Lead Engineer of Adiuvo Engineering & Training, Ltd.
Adam Taylor, CEng FIET, is a leading expert in embedded systems and FPGA design, including system-on-chip architectures, with applications in space, defense, and mission-critical systems. He has made significant contributions to image processing and secure communications. As Founder and Lead Engineer at Adiuvo Engineering & Training, Adam has delivered high-reliability FPGA solutions for major space missions, including ESA’s PLATO spacecraft. A Chartered Engineer, IEEE Senior Member, and IET Fellow, he is also a prolific educator, authoring books, technical papers, and a widely read engineering blog with over 30 million views.
Charles Lee Powell Chair in Engineering in the Ming Hsieh Department of Electrical and Computer Engineering and Professor of Computer Science at the University of Southern California
Viktor K. Prasanna (sites.usc.edu/prasanna) is Charles Lee Powell Chair in Engineering in the Ming Hsieh Department of Electrical and Computer Engineering and Professor of Computer Science at the University of Southern California. He is the director of the Center for Energy Informatics at USC and leads the FPGA (fpga.usc.edu) and Data Science Labs (dslab.usc.edu). His research interests include parallel and distributed computing, accelerator design, reconfigurable architectures and algorithms and high performance computing. He serves as the Editor-in-Chief of the Journal of Parallel and Distributed Computing. Prasanna was the founding Chair of the IEEE Computer Society Technical Committee on Parallel Processing. He is the Steering Chair of the IEEE International Parallel and Distributed Processing Symposium. He is a Fellow of the IEEE, the ACM and the American Association for Advancement of Science (AAAS). He is a recipient of 2009 Outstanding Engineering Alumnus Award from the Pennsylvania State University and a 2019 Distinguished Alumnus Award from the Indian Institute of Science. He received the 2015 W. Wallace McDowell award from the IEEE Computer Society for his contributions to reconfigurable computing. He is a member of Academia Europaea.