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Join the conversation shaping the future of FPGA technology! Embedded Computing Design presents an exclusive live roundtable series, bringing together industry leaders to explore where FPGA technology is headed, its groundbreaking applications, and how businesses can leverage its potential to stay ahead.
In this series, you'll see strategic and tactical discussions at the highest levels about how FPGAs are contributing to embedded computing advancements and streamlining the way embedded designs acheive computing goals.
Join the conversation shaping the future of FPGA technology! Embedded Computing Design presents an exclusive live roundtable series, bringing together industry leaders to explore where FPGA technology is headed, its groundbreaking applications, and how businesses can leverage its potential to stay ahead.
In this series, you'll see strategic and tactical discussions at the highest levels about how FPGAs are contributing to embedded computing advancements and streamlining the way embedded designs acheive computing goals.
Thu, Jun. 26, 2025 · 8:00 am (PDT)
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OEMs’ product portfolios often require offering a range of SKU variants with features and performance that would be difficult to service with a single FPGA device family. This creates unique challenges in scaling designs between different FPGA families.
For FPGA designs, scaling typically occurs between the prototype and production phases, allowing retargeting to a different device for adding or removing features/FPGA resources, or changes needed for performance/power reasons. A common architecture and extensive re-use of IP blocks within Altera’s Agilex™ 3 and 5 families allow scaling between families, offering designers more FPGA device options with which to innovate.
Whether you're new to FPGAs or an experienced designer, this session will help broaden your understanding of FPGA design considerations and how scaling occurs between Agilex 3 and 5 families. Join us as Altera and two Altera Solution Acceleration Partners, Terasic and iWave, share hands-on knowledge after having completed board designs for both the Agilex 5 (mid-range portfolio) and Agilex 3 (power & cost-optimized portfolio) FPGA and SoC families.
OEMs’ product portfolios often require offering a range of SKU variants with features and performance that would be difficult to service with a single FPGA device family. This creates unique challenges in scaling designs between different FPGA families.
For FPGA designs, scaling typically occurs between the prototype and production phases, allowing retargeting to a different device for adding or removing features/FPGA resources, or changes needed for performance/power reasons. A common architecture and extensive re-use of IP blocks within Altera’s Agilex™ 3 and 5 families allow scaling between families, offering designers more FPGA device options with which to innovate.
Whether you're new to FPGAs or an experienced designer, this session will help broaden your understanding of FPGA design considerations and how scaling occurs between Agilex 3 and 5 families. Join us as Altera and two Altera Solution Acceleration Partners, Terasic and iWave, share hands-on knowledge after having completed board designs for both the Agilex 5 (mid-range portfolio) and Agilex 3 (power & cost-optimized portfolio) FPGA and SoC families.
Sr. Director of Silicon Product Management and Marketing for Altera Corporation
Lux Joshi is a Sr. Director of Silicon Product Management and Marketing for Altera Corporation. He leads the go-to-market strategy and new product introduction for Altera’s Agilex FPGA and SoC portfolio. Lux has over 20 years of experience in the electronics industry, including over 13 years of experience with Altera. Prior to joining Altera, Lux held multiple roles in product development engineering for high-speed communications test equipment, covering end-to-end product design, including hardware design, validation, and manufacturing, and served as senior technical lead for multiple industry-leading products. Lux holds a Bachelor’s degree in Electrical Engineering from Columbia University, a Master’s degree in Electrical Engineering from Stanford University, and co-authored 3 patents in high-speed RF and digital design.
Sr. Managing Director at Terasic Inc.
Liz Chen is the Sr. Managing Director at Terasic Inc., leading global strategy for FPGA solutions. With over a decade of collaboration with Altera, she has brought to life some of the industry’s most recognized FPGA devkits—from Cyclone V and Stratix 10 to the latest Agilex 3, 5, and 7 series. Liz continues to drive Terasic’s global success across both low-cost and high-performance markets.
