WEBINAR DETAILS
  • About
    Learn from Altera and special guests, via a roundtable discussion, focusing on the productivity improvements enabled by the latest software tools for FPGA, AI, and embedded developers. Highlighted topics will include Altera’s new 4th generation system integration tool, Visual Designer Studio, along with a discussion about the importance of ‘DDR free’ mode for AI inference applications.

    This session is part of our FPGA Roundtable series. Registration/event page here.

    Sponsored by:
  • Duration
    1 hour
  • Price
    Free
  • Language
    English
  • OPEN TO
    Everyone
  • Dial-in available
    (listen only)
    Not available.
FEATURED PRESENTERS
  • Webinar hosting presenter

    Shreya Mehrotra

    Embedded and Memory Product Manager, Altera
    As an Embedded Software and Memory Product Manager, Shreya leads the marketing strategy and messaging for Altera's processor and peripheral IP portfolio, including RISC-V, ARM IP, and their embedded development suites, Visual Designer Studio...
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  • Webinar hosting presenter

    Hugh O’Keeffe

    CEO of Ashling
    Hugh O’Keeffe is CEO of Ashling and has spent over three decades working on embedded systems and development tools, including Ashling’s RiscFree™, a customizable SDK that supports creation, compilation, build, debug, test, and validation across...
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  • Webinar hosting presenter

    Alexander Montgomerie-Corcoran

    Co-Founder and CEO of Heronic Technologies
    Before starting the company, Alex completed his PhD at Imperial College London, researching methods for accelerating AI on FPGA devices. His research led to several publications, state-of-the-art benchmark results on MLPerf Tiny, and 1st place in...
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  • Webinar hosting presenter

    Ken Briodagh

    Editor in Chief Embedded Computing Design
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