Exploring FPGA Design: Practical Tips when Scaling between FPGA Families

OEMs’ product portfolios often require offering a range of SKU variants with features and performance that would be difficult to service with a single FPGA device family. This creates unique challenges in scaling designs between different FPGA families.   

For FPGA designs, scaling typically occurs between the prototype and production phases, allowing retargeting to a different device for adding or removing features/FPGA resources, or changes needed for performance/power reasons. A common architecture and extensive re-use of IP blocks within Altera’s Agilex™ 3 and 5 families allow scaling between families, offering designers more FPGA device options with which to innovate. 

Whether you're new to FPGAs or an experienced designer, this session will help broaden your understanding of FPGA design considerations and how scaling occurs between Agilex 3 and 5 families. Join us as Altera and two Altera Solution Acceleration Partners, Terasic and iWave, share hands-on knowledge after having completed board designs for both the Agilex 5 (mid-range portfolio) and Agilex 3 (power & cost-optimized portfolio) FPGA and SoC families.

This session is part of our FPGA Roundtable series. Registration/event page here.

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