Chiplets for High-Performance AI, aka the Datacenter and Edge Applications

AI workloads are outgrowing the capabilities of monolithic SoCs. Models are growing and inference is moving to the edge, while latency tolerance is shrinking and efficiency in compute, memory, and performance-per-watt are table stakes. This session will examine how chiplets are deployed for AI applications: partitioning compute, memory, and I/O across process nodes; integrating HBM and accelerator dies through advanced packaging; and scaling from rack-level training down to power-constrained edge inference. Attendees will leave knowing which chiplet strategies are shipping now, which are 12-24 months out, and what the tradeoffs mean for real designs.

This session is part of our “Chiplet Virtual Conference". Registration/event page here.